A datasheet lands on your desk for a sensor system, and the line that decides the project is the analog-to-digital converter. One option is 12-bit and cheap. Another is 16-bit and costs three times as much. The marketing copy talks about "high resolution" and "low noise," but those phrases are not numbers, and you have to defend a choice in a design review. What you really need is a way to turn the bit count into a signal quality you can compare against the noise floor of your sensor.
That bridge exists, and it is one short equation. It connects the number of bits in a converter directly to its signal-to-noise ratio, and once you know it, ADC selection stops being a guessing game.
Why this calculation matters
Every analog-to-digital converter does something subtly destructive: it rounds. A continuous voltage can take any value, but a converter must snap each reading to one of a finite set of levels. That rounding error is unavoidable, and it behaves like a small random noise added to every sample. It is called quantisation noise, and it sets a ceiling on the signal quality no converter can exceed, no matter how clean the rest of the system is.
This matters because the converter's resolution often decides whether a measurement is worth making. If your sensor produces a signal with a 70 dB dynamic range and you feed it into a converter with a 50 dB noise floor, the bottom 20 dB of real information is buried before any processing begins. Conversely, paying for a 16-bit converter when an 8-bit sensor is the weak link wastes money on quality you can never use. The resolution-to-SNR equation lets you match the converter to the signal, so you neither throw away information nor pay for headroom that does nothing.
The core formula
For an ideal N-bit analog-to-digital converter — one whose only error is quantisation — the best possible signal-to-noise ratio, measured with a full-scale sine-wave input, is:
SNR = 6.02 * N + 1.76 dB
Here N is the number of bits and SNR is the signal-to-noise ratio in decibels. The two constants come straight from the mathematics of quantisation, and it is worth seeing where they live.
The 6.02 per bit comes from the binary nature of resolution. Each extra bit halves the size of the quantisation step. A signal's power scales with the square of its amplitude, and halving the step quadruples the signal-to-noise power ratio. In decibels, a factor of four is 10 * log10(4) = 6.02 dB. So every bit you add is worth almost exactly 6 dB — that is the rule of thumb the whole equation rests on.
The 1.76 dB is a smaller correction. It arises because the equation compares the root-mean-square power of a full-scale sine wave against the RMS power of the quantisation noise, which is assumed to be uniformly spread across one step. The geometry of a sine relative to a flat noise distribution adds that fixed 1.76 dB offset, regardless of bit count.
A useful inversion of the same relationship works backward from a measured SNR to an effective resolution:
ENOB = (SNR - 1.76) / 6.02
ENOB is the effective number of bits. A real converter, with its own thermal noise, distortion, and clock jitter, always delivers an ENOB below its nominal N. Comparing the two is the honest way to read a datasheet.
A worked example
Take a 12-bit analog-to-digital converter and find its ideal SNR.
Step 1 — substitute the bit count.
SNR = 6.02 * N + 1.76
SNR = 6.02 * 12 + 1.76
Step 2 — evaluate the first term.
6.02 * 12 = 72.24 dB
This 72.24 dB is the contribution from the 12 bits of resolution alone — twelve steps of about 6 dB each.
Step 3 — add the sine-wave offset.
SNR = 72.24 + 1.76 = 74.0 dB
So an ideal 12-bit converter has a signal-to-noise ratio of 74.0 dB. That is the best it can ever do; quantisation noise alone caps it there, and any real-world imperfection only pulls it lower.
Step 4 — use it to compare. Suppose the next bit up, a 13-bit converter, is on the table. Its ideal SNR is 6.02 * 13 + 1.76 = 80.0 dB. The single extra bit bought 6.02 dB — exactly the per-bit step. If your sensor's own noise floor sits 76 dB below full scale, the 12-bit converter at 74 dB is the limiting element, and the upgrade to 13 bits is justified. If the sensor floor were at 70 dB, the 12-bit part already over-delivers and the extra bit is wasted. The equation turns a vague "is it good enough" into a direct comparison.
Common mistakes
Expecting a real converter to hit the ideal SNR. The 6.02 * N + 1.76 figure is a theoretical ceiling. Thermal noise, harmonic distortion, and clock jitter all subtract from it. A nominal 16-bit converter often delivers an ENOB of 13 to 14 bits in practice. Always design around the ENOB, not the marketing bit count.
Forgetting the formula assumes a full-scale input. The equation is derived for a sine wave that fills the converter's entire input range. A signal that uses only a quarter of the range loses about 12 dB of SNR straight away, because the quantisation noise is fixed while the signal got smaller. Use as much of the input range as you safely can.
Treating jitter as negligible. At high input frequencies, uncertainty in the sampling instant — clock jitter — adds its own noise that has nothing to do with bit count. A converter can be jitter-limited long before it is resolution-limited, and adding bits will not help in that regime.
Confusing dynamic range with SNR. They are related but not identical. SNR is measured with a signal present; dynamic range describes the span from the largest usable signal to the smallest detectable one. Datasheets sometimes quote whichever number looks better, so check which one you are reading.
Assuming more bits always means a better measurement. Resolution is only one link in the chain. If the sensor, the amplifier, or the reference voltage is the noisiest element, extra converter bits resolve nothing but noise. Find the weakest link first, then size the converter to it.
Try the interactive NovaSolver calculator
Seeing how quantisation noise and timing jitter trade off is far clearer when you can move the parameters and watch the SNR respond. The ADC Sampling Jitter SNR Simulator on NovaSolver lets you set the input frequency, sampling rate, clock jitter, and bit depth with sliders, and it returns the jitter-limited SNR, the quantisation SNR, the combined SNR, and the effective number of bits — alongside waveform samples, an SNR curve, and an error-cloud plot that shows where the noise is coming from.
Related calculators
- Nyquist Sampling Theorem Simulator — pair resolution with sample rate so your converter neither aliases nor undersamples.
- Sampling Theorem & Aliasing Visualizer — watch how sample timing turns a continuous wave into discrete points.
- FFT Spectrum Analyzer — see the quantisation noise floor directly in a measured frequency spectrum.
You can browse the rest in the frequency response and stability tools hub.
Closing note
The relationship SNR = 6.02 * N + 1.76 dB is small enough to memorise and powerful enough to settle most ADC arguments. Each bit is worth about 6 dB, the 1.76 dB is the sine-wave bookkeeping term, and the whole figure is a theoretical best that real hardware only approaches. Use it to translate a bit count into a noise floor, compare that floor to your sensor's own, and let the weakest link in the chain decide the resolution you actually need. That is how a datasheet number becomes an engineering decision you can defend.
