Software gets to retry. A traffic signal at rush hour does not.
Most of us build in a world with a safety net — a request fails, you try again, nobody notices. Move down to hardware controlling something physical and that net disappears. The signal has to make the right decision this cycle, in real time, every time, because there is no "please refresh."
So imagine signal timing that adapts to actual traffic on the silicon itself — reading demand and adjusting green time cycle by cycle, with no processor, no operating system, and no network call in the loop. Determinism stops being a nice-to-have and becomes the whole point: the logic does exactly one thing, exactly on time.
That's what I implemented as an FPGA-based adaptive traffic controller in Verilog — real-time signal timing that adjusts to demand to improve throughput, running entirely in hardware. Writing for an FPGA rewires how you think: you're not writing instructions that execute in sequence, you're describing circuits that all exist at once.
It's a useful discipline to borrow even in software. When you can't retry, you're forced to actually get it right — and that constraint makes better engineers.
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